پیاده سازی ALU

در این مثال می خواهیم یک ALU را بر روی یک FPGA پیاده سازی کنیم.
 
در زیر کد VHDL مربوط به برنامه ALU آورده شده است.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_logic_signed.all;

 

entity ALU is

     port(

         A : in STD_LOGIC_VECTOR(7 downto 0);

         B : in STD_LOGIC_VECTOR(7 downto 0);

         Sel : in STD_LOGIC_VECTOR(3 downto 0);

         Cin : in STD_LOGIC;

         y : out STD_LOGIC_VECTOR(7 downto 0)

         );

end ALU;

---------------------------------------------------

architecture Behavioural of ALU is

signal arith,logic: STD_LOGIC_VECTOR(7 downto 0);

----------------------------------------------------

begin

----------------ARITHMETIC UNIT---------------------

WITH sel(2 downto 0) select

  arith<=A      when "000",

          A+1   when "001",

          A-1   when "010",

          B     when "011",

          B+1   when "100",

          B-1   when "101",

          A+B   when "110",

       A+B+Cin  when OTHERS;

-----------------LOGIC UNIT-------------------------- 

  WITH sel(2 downto 0) select

 

        LOGIC<= NOT A        when "000",

                NOT B        when "001",

                A AND B      when "010",

                A OR B       when "011",

                A NAND B     when "100",

                A NOR B      when "101",

                A XOR B      when "110",

                NOT(A XOR B) when OTHERS;

-----------------------MUX----------------------------

WITH SEL (3) SELECT

                 

 Y<= ARITH WHEN '0',

 

 LOGIC    WHEN OTHERS;

 

END Behavioural;


 

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